The present invention relates to a technique which is effective when applied to a semiconductor integrated circuit device (or a semiconductor device) in which plural types of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) having different breakdown voltages are integrated.
Each of Japanese Unexamined Patent Publication No. 2002-170888 (Patent Document 1) and U.S. Pat. No. 6,780,717 (Patent Document 2) discloses a semiconductor integrated circuit device in which two types of MISFETs having a low breakdown voltage and a high breakdown voltage, respectively, are integrated. In the high-breakdown-voltage MISFET, a gate electrode has an entire periphery thereof overlying a high-breakdown-voltage gate insulating film formed by CVD.
Japanese Unexamined Patent Publication No. 2005-340627 (Patent Document 3) discloses a technique which couples a gate electrode directly to a substrate to form a path for accumulated charges in order to prevent a dielectric breakdown in a lower-layer gate insulating film which occurs during the plasma etching of a metal wiring in the manufacturing process of a semiconductor integrated circuit device in which typical MISFETs are integrated. In the publication, there is shown a structure in which a gate electrode extending beyond the end portion of a gate insulating film deposited over a substrate has a portion coupled to a contact electrode outside a region covered with the gate insulating film.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2002-170888[Patent Document 2]    U.S. Pat. No. 6,780,717[Patent Document 3]    Japanese Unexamined Patent Publication No. 2005-340627